The present invention relates to a design of a computer system that processes interrupt signals. Furthermore, the present invention relates to methods for operating a computer system controlled by a central processing unit in which the computer system processes interrupt signals. In particular, the present invention relates to an interrupt verification support mechanism to verify and to handle such interrupt signals and a method for operating the mechanism.
Methods of this type are used for example in real-time computer systems utilized in telecommunication modules of public and private networks and in general purpose computer systems utilized in personal computers. In a real-time computer system the processing of a program activated, for example as a reaction to an interrupt signal can be interrupted within a determined limited time interval, in order to continue the processing of this program only when higher-priority programs have been processed. During the processing of a program, e.g. in telecommunication modules, several thousand interrupt signals per second can occur, which respectively require an interruption of a program to be processed at that time and a reaction to the interrupt signal.
Known computer systems block the acceptance of further interrupt signals for a predetermined time interval, called the interrupt blocking time, so that interrupt signals coming in during this time interval are not taken into account is processed, and information or instructions can be lost. The interrupt blocking time is required so that the microprocessor can secure its registers, can react at least partly to the interrupt signal, and can again update its registers in order to be able to continue the interrupted program. The longer this interrupt blocking time is, all the more incoming interrupt signals go without being processed. It is therefore desirable to develop a computer operating system component that permits the acquisition of, and reaction to the highest possible number of occurring interrupt signals per time unit. In this context, In order to verify that an interrupt processing system operates correctly, it is necessary to ensure that interrupts have been correctly processed in a large number of circumstances. Some of these circumstances are very rare and require the timing of the interrupt to be timed precisely.
A common way to implement interrupts in a processor is to transform a respective instruction into a pseudo-interrupt instruction at a specific point in the process flow of the computer system. This means that, instead of behaving like, e.g., an arithmetic instruction, the instruction will perform the state changes associated with an interrupt, which is typically a branch with some associated changes to the processor state.
Interrupt verification usually relies on an external interrupt generator that is part of the test bench when a design is being verified. The timing of these interrupts can be performed either uncontrolled or controlled by fixed timings. A definition of the precise point at which an interrupt strikes in a stream of instructions that are run on a processor cannot be achieved by an uncontrolled timing of interrupts, since the timing is likely to vary and it does not allow the same test to be reproduced. A timing of interrupts controlled by fixed timings might obtain a determined point of interruption of the instruction flow, but is liable to change when the timing of internal signals changes, e.g. when a bug is fixed. Furthermore, a timing of interrupts controlled by fixed timings is hard to control because of the speed at which the external interrupt generator would have to run. A timing of interrupts controlled by probing signals inside the design cannot be run on silicon due to the impossibility of probing signals inside the respective silicon itself.
Therefore, in one variant of the invention a device and a corresponding method which is able to define the precise point at which an interrupt strikes in a stream of instructions that are run on a processor. In another variant of the invention, a device and a corresponding method which is able to reliably reproduce the same test running results on the silicon design as in a simulation. In yet another variant a computer, computer system comprising one or more computers, utilize the device and method described herein.